31 lines
504 B
Plaintext
31 lines
504 B
Plaintext
// File : tb_top.sv
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module tb_top ();
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reg clk;
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reg resetn;
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reg d;
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wire q;
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// Instantiate the design
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d_ff d_ff0 ( .clk (clk),
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.resetn (resetn),
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.d (d),
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.q (q));
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// Create a clock
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always #10 clk <= ~clk;
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initial begin
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resetn <= 0;
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d <= 0;
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#10 resetn <= 1;
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#5 d <= 1;
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#8 d <= 0;
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#2 d <= 1;
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#10 d <= 0;
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end
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endmodule
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// From https://www.chipverify.com/tutorials/systemverilog
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