44 lines
1.2 KiB
Plaintext
44 lines
1.2 KiB
Plaintext
-- dual_port_RAM_visualTest.vhd
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-- created by : Meher Krishna Patel
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-- date : 26-Dec-16
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-- Functionality:
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-- store and retrieve data from dual port RAM
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-- ports:
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-- Write Enable (we) : SW[16]
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-- Address (addr_wr) : SW[15-14]
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-- Address (addr_rd) : SW[13-12]
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-- din : SW[2:0]
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-- dout : LEDR
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use ieee.numeric_std.all;library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity dual_port_RAM_visualTest is
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generic (
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ADDR_WIDTH : integer := 2;
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DATA_WIDTH : integer := 3
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);
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port(
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CLOCK_50: in std_logic;
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SW : in std_logic_vector(16 downto 0);
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LEDR : out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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end dual_port_RAM_visualTest;
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architecture arch of dual_port_RAM_visualTest is
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begin
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dual_port_RAM_test: entity work.dual_port_RAM
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port map (clk=>CLOCK_50, we=>SW(16),
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addr_wr => SW(15 downto 14),
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addr_rd => SW(13 downto 12),
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din => SW(2 downto 0),
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dout =>LEDR);
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end arch;
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-- From https://vhdlguide.readthedocs.io/en/latest/vhdl/dex.html
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